Towards the Electron Holography of Working Transistors

Sadegh Yazdi
Project coordinators: David W. Mc-Comb, Alison C. Harrison (Imperial College London)
Staff at DTU Cen: Takeshi Kasama
Funding: EPSRC
The need for mapping electrostatic potentials, which are responsible for the functionality of electronic devices, at high spatial resolution in 2-D and 3-D has been highlighted recently in the International Technology Roadmap for Semiconductors (ITRS). The aim of this project is to examine the electrostatic potential within the nanoscale semiconductor devices under “working conditions”, i.e. under a bias field. Advanced electron microscopy techniques including electron holography, scanning electron microscopy and transmission elec-tron beam induced current microscopy (EBIC) are involved in this project in order to understand the distribution of the electrostatic potential. To minimize the specimen preparation artifacts, a state-of-the-art dual beam workstation (FIB/SEM) is being used at low voltages

to develop a protocol for the formation of site-specific TEM sections.For the application of the electrical bias to the devices seat in these sections, the capability of the focused ion beam in the maskless deposition is employed.


Phase images reconstructed from off-axis electron holograms of 0.18 um a) n-MOS and b) p-MOS transistors. The lectrostatic potential in the source and drain regions of the p-MOS is smaller than the n-type substrate, therefore these regions are darker than the substrate.
26 FEBRUARY 2020